K Notice that the outputs change on the leading edge of the clock.
Q Summary Flip-flops Q J Example CLK Determine the Q output for the J-K flip-flop, given the inputs shown. When both J and K = 1, the output changes states (toggles) on the active clock edge (in this case, the rising edge). In addition to the clock input, it has two inputs, labeled J and K. Summary Flip-flops The J-K flip-flop is more versatile than the D flip flop. (a) Positive-edge triggered (b) Negative-edge triggered The truth table for a negative-edge triggered D flip-flop is identical except for the direction of the arrow. Summary Flip-flops The truth table for a positive-edge triggered D flip-flop shows an up arrow to remind you that it is sensitive to its D input only on the rising edge of the clock otherwise it is latched. The active edge can be positive or negative. A flip-flop is a clocked device, in which only the clock edge determines when a new bit is entered. Summary Flip-flops A flip-flop differs from a latch in the manner it changes states. Summary Latches Q D Example EN Determine the Q output for the D latch, given the inputs shown. Q Notice that the Enable is not active during these times, so the output is latched. If EN is LOW, then there is no change in the output and it is latched. Summary Latches The truth table for the D latch summarizes its operation. Q Q Summary Latches The D latch is an variation of the S-R latch but combines the S and R inputs into a single D input as shown: D Q D Q EN EN A simple rule for the D latch is: Q follows D when the Enable is active. Example R Solution Keep in mind that S and R are only active when EN is HIGH. S Q EN Show the Q output with relation to the input signals. The gated latch has an additional input, called enable (EN) that must be HIGH in order for the latch to respond to the S and R inputs. Q Summary Latches A gated latch is a variation on the basic latch. S-R latches are frequently used for switch debounce circuits as shown: VCC Q S Position 1 to 2 Position 2 to 1 R S R Summary Latches The active-LOW S-R latch is available as the 74LS279A IC. To SET any of the latches, the S line is pulsed low. It features four internal latches with two having two S inputs.
1 0 1 Q Latch initially RESET 1 0 1 1 0 1 Q Latch initially SET Never apply an active set and reset at the same time (invalid). Q Q R Summary Latches The active-LOW S-R latch is in a stable (latched) condition when both inputs are HIGH. S R S To RESET the latch a momentary LOW is applied to the R input while S is HIGH. To SET the latch (Q = 1), a momentary LOW signal is applied to the S input while the R remains HIGH. Latch initially SET 0 1 0Īssume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (1). Latch initially RESET 1 0 0 0 0 1 To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while the S remains LOW. To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while the R remains LOW. 0 0 1 Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (0). R R Q Q S S Q Q Summary Latches The active-HIGH S-R latch is in a stable (latched) condition when both inputs are LOW.
R Q Q S NOR Active-HIGH Latch NAND Active-LOW Latch
With NOR gates, the latch responds to active-HIGH inputs with NAND gates, it responds to active-LOW inputs. It can be constructed from NOR gates or NAND gates. The S-R (Set-Reset) latch is the most basic type. S Q Q R Summary Latches A latch is a temporary storage device that has two stable states (bistable). Digital Fundamentals Tenth Edition Floyd Chapter 7 © 2008 Pearson Education